LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AC_C is ---
port (
		LOAD_C : IN STD_LOGIC; ---
		clk : IN STD_LOGIC;
		Data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		C : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ---
);
end AC_C; ---

ARCHITECTURE accu OF AC_C IS ---

BEGIN

  PROCESS(clk,LOAD_C,data_in) ---
   BEGIN
	IF clk'event AND clk = '1' THEN 
		IF LOAD_C = '1' THEN  ---
		C <= Data_in; ---
		END IF;
	END IF;
	
  END PROCESS;

END accu;